Low-latency digit-serial dual basis multiplier for...

IET Information Security 2017 / 11 Vol. 11; Iss. 6

Low-latency digit-serial dual basis multiplier for lightweight cryptosystems

Chiou, Che Wun, Lee, Chiou-Yng, Lin, Jim-Min, Yeh, Yun-Chi, Pan, Jeng-Shyang
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Volume:
11
Language:
english
Journal:
IET Information Security
DOI:
10.1049/iet-ifs.2015.0336
Date:
November, 2017
File:
PDF, 2.71 MB
english, 2017
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