On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC...

IEICE Transactions on Electronics 2009 Vol. E92-C; Iss. 3

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform

SHIMANO, Hiroki, MORISHITA, Fukashi, DOSAKA, Katsumi, ARIMOTO, Kazutami
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Volume:
E92-C
Year:
2009
Language:
english
Journal:
IEICE Transactions on Electronics
DOI:
10.1587/transele.e92.c.356
File:
PDF, 1.23 MB
english, 2009
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