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[IEEE 2017 International Electrical Engineering Congress (iEECON) - Pattaya, Thailand (2017.3.8-2017.3.10)] 2017 International Electrical Engineering Congress (iEECON) - Throughput of a firewall unit on FPGAs developed by the RTL design methodology

Sato, Tomoaki, Chivapreecha, Sorawat, Moungnoul, Phichet, Higuchi, Kohji
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Year:
2017
DOI:
10.1109/IEECON.2017.8075819
File:
PDF, 2.26 MB
2017
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