Vector Processing-Aware Advanced Clock-Gating Techniques...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic, Ivan, Palomar, Oscar, Stanic, Milan, Unsal, Osman Sabri, Cristal, Adrian, Valero, Mateo
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2017.2784807
File:
PDF, 2.86 MB
english, 2018
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