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[IEEE 2017 Symposium on VLSI Circuits - Kyoto, Japan (2017.6.5-2017.6.8)] 2017 Symposium on VLSI Circuits - An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz
Hummerston, Derek, Hurrell, PeterYear:
2017
Language:
english
DOI:
10.23919/VLSIC.2017.8008508
File:
PDF, 1.04 MB
english, 2017