Self Clock-Gating Scheme for Low Power Basic Logic Element...

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Wireless Personal Communications 2018 / 2

Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture

Udaiyakumar, R., Joseph, Senoj, Sundararajan, T. V. P., Vigneswaran, D., Maheswar, R., Amiri, Iraj S.
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Language:
english
Journal:
Wireless Personal Communications
DOI:
10.1007/s11277-018-5385-2
Date:
February, 2018
File:
PDF, 975 KB
english, 2018
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