Compact Model for Double-Gate Tunnel FETs With Gate–Drain...

IEEE Transactions on Electron Devices 2017 / 12 Vol. 64; Iss. 12

Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

Xu, Peng, Lou, Haijun, Zhang, Lining, Yu, Zhonghua, Lin, Xinnan
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Volume:
64
Language:
english
Journal:
IEEE Transactions on Electron Devices
DOI:
10.1109/TED.2017.2762861
Date:
December, 2017
File:
PDF, 1.10 MB
english, 2017
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