[IEEE 2017 IEEE 12th International Conference on ASIC (ASICON) - Guiyang (2017.10.25-2017.10.28)] 2017 IEEE 12th International Conference on ASIC (ASICON) - Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design
Yang, Jianwei, Wang, Weizhen, Xie, Zhicheng, Han, Jun, Yu, Zhiyi, Zeng, XiaoyangYear:
2017
Language:
english
DOI:
10.1109/ASICON.2017.8252635
File:
PDF, 377 KB
english, 2017