[IEEE 2017 IEEE SOI-3D-Subthreshold Microelectronics...

  • Main
  • [IEEE 2017 IEEE SOI-3D-Subthreshold...

[IEEE 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) - Burlingame, CA, USA (2017.10.16-2017.10.19)] 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) - An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Yamamoto, Yoshiki, Hasegawa, Takumi, Yabuuchi, Makoto, Nii, Koji, Sawada, Yohei, Tanaka, Shinji, Shinozaki, Yoshihiro, Ito, Kyoji, Shinkawata, Hiroki, Kamohara, Shiro
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Year:
2017
Language:
english
DOI:
10.1109/S3S.2017.8309224
File:
PDF, 1.68 MB
english, 2017
Conversion to is in progress
Conversion to is failed