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[IEEE 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Pune, India (2018.1.6-2018.1.10)] 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) - Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique
Aketi, Sai Aparna, Mekie, Joycee, Shah, HemalYear:
2018
Language:
english
DOI:
10.1109/VLSID.2018.71
File:
PDF, 820 KB
english, 2018