![](/img/cover-not-exists.png)
Design for Delay Fault Testability of 2-Rail Logic Circuits
KATOH, Kentaroh, NAMBA, Kazuteru, ITO, HideoVolume:
E92-D
Year:
2009
Language:
english
Journal:
IEICE Transactions on Information and Systems
DOI:
10.1587/transinf.e92.d.336
File:
PDF, 455 KB
english, 2009