Design for Delay Fault Testability of 2-Rail Logic Circuits

Design for Delay Fault Testability of 2-Rail Logic Circuits

KATOH, Kentaroh, NAMBA, Kazuteru, ITO, Hideo
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Volume:
E92-D
Year:
2009
Language:
english
Journal:
IEICE Transactions on Information and Systems
DOI:
10.1587/transinf.e92.d.336
File:
PDF, 455 KB
english, 2009
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