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A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS
Ramkaj, Athanasios T., Strackx, Maarten, Steyaert, Michiel S. J., Tavernier, FilipYear:
2018
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2018.2822823
File:
PDF, 4.63 MB
english, 2018