Bit-Level Load Balancing: A New Technique for Improving the...

IEEE Computer Architecture Letters 2018 / 7 Vol. 17; Iss. 2

Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM

Ipek, Engin, Longnos, Florian, Xiao, Shihai, Yang, Wei
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Volume:
17
Language:
english
Journal:
IEEE Computer Architecture Letters
DOI:
10.1109/LCA.2018.2819979
Date:
July, 2018
File:
PDF, 338 KB
english, 2018
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