Tolerating Soft Errors in Processor Cores Using CLEAR...

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2017

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

Cheng, Eric, Mirkhani, Shahrzad, Szafaryn, Lukasz G., Cher, Chen-Yong, Cho, Hyungmin, Skadron, Kevin, Stan, Mircea R., Lilja, Klas, Abraham, Jacob A., Bose, Pradip, Mitra, Subhasish
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Year:
2017
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/TCAD.2017.2752705
File:
PDF, 816 KB
english, 2017
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