Ultra-low power source coupled FET logic gate configuration...

Electronics Letters 2000 Vol. 36; Iss. 1

Ultra-low power source coupled FET logic gate configuration in GaAs MESFET technology

Bushehri, E., Bratov, V., Starosselski, V., Schlichter, T., Milenkovic, S., Timochenkov, V.
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Volume:
36
Year:
2000
Language:
english
Journal:
Electronics Letters
DOI:
10.1049/el:20000016
File:
PDF, 318 KB
english, 2000
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