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[IEEE 2016 20th International Symposium on VLSI Design and Test (VDAT) - Guwahati, India (2016.5.24-2016.5.27)] 2016 20th International Symposium on VLSI Design and Test (VDAT) - Guided shifting of test pattern to minimize test time in serial scan
Tudu, Jaynarayan T, Ahlawat, SatyadevYear:
2016
Language:
english
DOI:
10.1109/ISVDAT.2016.8064851
File:
PDF, 203 KB
english, 2016