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[IEEE 2017 Forum on Specification and Design Languages (FDL) - Verona (2017.9.18-2017.9.20)] 2017 Forum on Specification and Design Languages (FDL) - Automatic generation of cycle-accurate Simulink blocks from hdl ips
Centomo, Stefano, Lora, Michele, Portaluri, Antonio, Stefanni, Francesco, Fummi, FrancoYear:
2017
Language:
english
DOI:
10.1109/fdl.2017.8303896
File:
PDF, 97 KB
english, 2017