High Speed and Efficient Area Optimal Ate Pairing Processor...

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High Speed and Efficient Area Optimal Ate Pairing Processor Implementation over BN and BLS12 Curves on FPGA

Sghaier, Anissa, Zeghid, Medien, Ghammam, Loubna, Duquesne, Sylvain, Machhout, Mohsen, Ahmed, Hassan Yousif
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Language:
english
Journal:
Microprocessors and Microsystems
DOI:
10.1016/j.micpro.2018.06.001
Date:
June, 2018
File:
PDF, 2.48 MB
english, 2018
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