A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop
Wang, Chua-Chin, Chien, Yu-Tsun, Chen, Ying-PeiVolume:
11
Year:
2000
Language:
english
Journal:
VLSI Design
DOI:
10.1155/2000/52658
File:
PDF, 3.13 MB
english, 2000