[IFIP Advances in Information and Communication Technology] System Level Design from HW/SW to Memory for Embedded Systems Volume 523 || Low Latency FPGA Implementation of Izhikevich-Neuron Model
Götz, Marcelo, Schirner, Gunar, Wehrmeister, Marco Aurélio, Al Faruque, Mohammad Abdullah, Rettberg, AchimVolume:
10.1007/97
Year:
2017
Language:
english
DOI:
10.1007/978-3-319-90023-0_17
File:
PDF, 662 KB
english, 2017