A Modified Approach to Test Plan Generation for...

A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Basu, Anupam, Banerji, Dilip K., Basu, Amit, Wilson, T. C., Majithia, Jay C.
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Volume:
4
Year:
1996
Language:
english
Journal:
VLSI Design
DOI:
10.1155/1996/37648
File:
PDF, 2.63 MB
english, 1996
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