Embedded Parity and Two-Rail TSC Checkers with...

Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability

Tarnick, Steffen
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Volume:
5
Year:
1998
Language:
english
Journal:
VLSI Design
DOI:
10.1155/1998/67574
File:
PDF, 2.52 MB
english, 1998
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