A Spatial Multi-bit Sub-1V Time-Domain Matrix Multiplier...

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2018

A Spatial Multi-bit Sub-1V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65nm CMOS

Gopal, Srinivasan, Agarwal, Pawan, Baylon, Joe, Renaud, Luke, Ali, Sheikh Nijam, Pande, Partha Pratim, Heo, Deukhyoun
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Year:
2018
Language:
english
Journal:
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
DOI:
10.1109/JETCAS.2018.2852624
File:
PDF, 1.10 MB
english, 2018
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