The Design and Implementation of a Low-Power Gating Scan...

Journal of Low Power Electronics and Applications 2017 / 04 Vol. 7; Iss. 2

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini, Mahshid, Dass, Sreedharan, Ooi, Chia
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Volume:
7
Language:
english
Journal:
Journal of Low Power Electronics and Applications
DOI:
10.3390/jlpea7020007
Date:
April, 2017
File:
PDF, 2.16 MB
english, 2017
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