Two-stage low power test data compression for digital VLSI...

Computers & Electrical Engineering 2018 / 10 Vol. 71

Two-stage low power test data compression for digital VLSI circuits

Thilagavathi, K., Sivanantham, S.
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
71
Language:
english
Journal:
Computers & Electrical Engineering
DOI:
10.1016/j.compeleceng.2018.07.009
Date:
October, 2018
File:
PDF, 803 KB
english, 2018
Conversion to is in progress
Conversion to is failed