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[IEEE 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Hong Kong (2018.7.8-2018.7.11)] 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Timing Macro Modeling for Efficient Hierarchical Timing Analysis
Jiang, Iris Hui-Ru, Lee, Pei-YuYear:
2018
DOI:
10.1109/ISVLSI.2018.00134
File:
PDF, 215 KB
2018