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[IEEE 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Dresden (2018.3.19-2018.3.23)] 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - A parameterized timing-aware flip-flop merging algorithm for clock power reduction
Feng, Chaochao, Yue, Daheng, Zhao, Zhenyu, Liao, ZhuofanYear:
2018
Language:
english
DOI:
10.23919/DATE.2018.8342131
File:
PDF, 118 KB
english, 2018