A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration

Enomoto, Ryuichi, Iizuka, Tetsuya, Koga, Takehisa, Nakura, Toru, Asada, Kunihiro
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2018.2867505
File:
PDF, 2.85 MB
english, 2018
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