![](/img/cover-not-exists.png)
[IEEE 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Platja d'Aro, Spain (2018.7.2-2018.7.4)] 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) - UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog
Georgoulopoulos, Nikolaos, Giannou, Ioannis, Hatzopoulos, AlkiviadisYear:
2018
DOI:
10.1109/patmos.2018.8464148
File:
PDF, 639 KB
2018