Design and Implementation of Hybrid Multiple Valued Logic...

IOP Conference Series Materials Science and Engineering 2017 / 08 Vol. 225

Design and Implementation of Hybrid Multiple Valued Logic Error Detector using Single Electron Transistor and CMOS at 120nm Technology

Raut, Vaishali P., Dakhole, P.k.
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Volume:
225
Language:
english
Journal:
IOP Conference Series: Materials Science and Engineering
DOI:
10.1088/1757-899X/225/1/012160
Date:
August, 2017
File:
PDF, 1.59 MB
english, 2017
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