Design considerations and optimisation of clock circuit for...

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Australian Journal of Electrical & Electronics Engineering 2018 / 10

Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications

Walunj, R. A., Pable, S. D., Kharate, G. K.
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Language:
english
Journal:
Australian Journal of Electrical and Electronics Engineering
DOI:
10.1080/1448837X.2018.1527101
Date:
October, 2018
File:
PDF, 3.26 MB
english, 2018
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