SoC interconnection protection through formal verification

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Integration, the VLSI Journal 2018 / 10

SoC interconnection protection through formal verification

He, Jiaji, Guo, Xiaolong, Meade, Travis, Dutta, Raj Gautam, Zhao, Yiqiang, Jin, Yier
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Language:
english
Journal:
Integration
DOI:
10.1016/j.vlsi.2018.09.007
Date:
October, 2018
File:
PDF, 965 KB
english, 2018
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