Formal Modeling and Verification of Controllers for a...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018 / 11 Vol. 37; Iss. 11

Formal Modeling and Verification of Controllers for a Family of DRAM Caches

Sahoo, Debiprasanna, Sha, Swaraj, Satpathy, Manoranjan, Mutyam, Madhu, Ramesh, S., Roop, Partha
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Volume:
37
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/TCAD.2018.2857318
Date:
November, 2018
File:
PDF, 2.44 MB
english, 2018
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