Area-Delay-Energy Efficient VLSI Architecture for Scalable...

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IEEE Transactions on Circuits and Systems I: Regular Papers 2018

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Mohanty, Basant K., Meher, Pramod Kumar
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/TCSI.2018.2873720
File:
PDF, 2.88 MB
english, 2018
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