Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced...

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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Gupta, Shourya, Gupta, Kirti, Calhoun, Benton H., Pandey, Neeta
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/TCSI.2018.2876785
File:
PDF, 4.14 MB
english, 2018
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