A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted...

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IEEE Journal of Solid-State Circuits 2018

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS

Kiran, Shiva, Cai, Shengchang, Luo, Ying, Hoyos, Sebastian, Palermo, Samuel
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Year:
2018
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2018.2878850
File:
PDF, 4.87 MB
english, 2018
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