Resistive RAM With Multiple Bits Per Cell: Array-Level...

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IEEE Transactions on Electron Devices 2018

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Le, Binh Q., Grossi, Alessandro, Vianello, Elisa, Wu, Tony, Lama, Giusy, Beigne, Edith, Wong, H.-S. Philip, Mitra, Subhasish
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Electron Devices
DOI:
10.1109/TED.2018.2879788
File:
PDF, 2.66 MB
english, 2018
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