An Area-Efficient 128-Channel Spike Sorting Processor for...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175 μW/Channel in 65-nm CMOS

Do, Anh Tuan, Zeinolabedin, Seyed Mohammad Ali, Jeon, Dongsuk, Sylvester, Dennis, Kim, Tony Tae-Hyoung
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Year:
2018
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2018.2875934
File:
PDF, 3.34 MB
english, 2018
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