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An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 x 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
Taco, Ramiro, Levi, Itamar, Lanuzza, Marco, Fish, AlexanderYear:
2018
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2018.2882139
File:
PDF, 4.39 MB
english, 2018