IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
2019 / 1 Vol. E102.A; Iss. 1
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An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field
AWANO, Hiromitsu, ICHIHASHI, Tadayuki, IKEDA, MakotoVolume:
E102.A
Language:
english
Journal:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
DOI:
10.1587/transfun.E102.A.56
Date:
January, 2019
File:
PDF, 2.70 MB
english, 2019