Three Dimensional FPGA Architecture with Fewer TSVs

IEICE Transactions on Information and Systems 2018 Vol. E101.D; Iss. 2

Three Dimensional FPGA Architecture with Fewer TSVs

AMAGASAKI, Motoki, IKEBE, Masato, ZHAO, Qian, IIDA, Masahiro, SUEYOSHI, Toshinori
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Volume:
E101.D
Year:
2018
Language:
english
Journal:
IEICE Transactions on Information and Systems
DOI:
10.1587/transinf.2017RCP0008
File:
PDF, 1.50 MB
english, 2018
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