![](/img/cover-not-exists.png)
[IEEE 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2019.2.17-2019.2.21)] 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
Kim, Juyeop, Yoon, Heein, Lim, Younghyun, Lee, Yongsun, Cho, Yoonseo, Seong, Taeho, Choi, JaehyoukYear:
2019
Language:
english
DOI:
10.1109/ISSCC.2019.8662532
File:
PDF, 439 KB
english, 2019