![](/img/cover-not-exists.png)
[IEEE 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2019.2.17-2019.2.21)] 2019 IEEE International Solid- State Circuits Conference - (ISSCC) - 24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue
Fujiwara, Hidehiro, Lin, Chih-Yu, Pan, Hsien-Yu, Lin, Cheng-Han, Huang, Po-Yi, Lin, Kao-Cheng, Liaw, Jhon-Jhy, Chen, Yen-Huei, Liao, Hung-Jen, Chang, JonathanYear:
2019
Language:
english
DOI:
10.1109/ISSCC.2019.8662415
File:
PDF, 365 KB
english, 2019