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Microelectronic Engineering 2019 / 5

Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework

Garzon, Esteban, De Rose, Raffaele, Crupi, Felice, Trojman, Lionel, Lanuzza, Marco
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Language:
english
Journal:
Microelectronic Engineering
DOI:
10.1016/j.mee.2019.111009
Date:
May, 2019
File:
PDF, 1.78 MB
english, 2019
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