[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature
Nirmalkar, Tripti, Kanoujia, Deepti, Varma, KshitizYear:
2019
Language:
english
DOI:
10.1109/VLSID.2019.00029
File:
PDF, 318 KB
english, 2019