[IEEE 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Noida, India (2019.3.7-2019.3.8)] 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) - Power Reduction in Domino Logic Using Clock Gating in 16nm CMOS Technology
Singhal, Smita, Mehra, Anu, Tripathi, UpendraYear:
2019
Language:
english
DOI:
10.1109/SPIN.2019.8711713
File:
PDF, 144 KB
english, 2019