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IEEE Transactions on Semiconductor Manufacturing 2019

Cost-effective and Time-efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer

Yanagita, Hiroshi, Jingu, Akihito, Okanishi, Shinobu, Tanaka, Satoshi, Koyama, Toru
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Year:
2019
Language:
english
Journal:
IEEE Transactions on Semiconductor Manufacturing
DOI:
10.1109/tsm.2019.2934115
File:
PDF, 705 KB
english, 2019
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