Joint background calibration of gain and timing mismatch errors with low hardware cost for time-interleaved ADCs
Zhang, Jie, Zhang, Hong, Yang, Bo, Zhang, RuizhiVolume:
13
Journal:
IET Circuits, Devices & Systems
DOI:
10.1049/iet-cds.2018.5194
Date:
March, 2019
File:
PDF, 33 KB
2019