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[IEEE 2019 Symposium on VLSI Circuits - Kyoto, Japan (2019.6.9-2019.6.14)] 2019 Symposium on VLSI Circuits - A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator
Bindra, Harijot Singh, Annema, Anne-Johan, Louwsma, Simon M., Nauta, BramYear:
2019
DOI:
10.23919/VLSIC.2019.8778093
File:
PDF, 163 KB
2019