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[IEEE 2019 Symposium on VLSI Circuits - Kyoto, Japan (2019.6.9-2019.6.14)] 2019 Symposium on VLSI Circuits - Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array
Kim, Jinseok, Koo, Jongeun, Kim, Taesu, Kim, Yulhwa, Kim, Hyungjun, Yoo, Seunghyun, Kim, Jae-JoonYear:
2019
Language:
english
DOI:
10.23919/VLSIC.2019.8778160
File:
PDF, 202 KB
english, 2019